1. Field of the Invention
The present invention relates to integrated circuit CMOS technology and more particularly to a method and means for controlling the voltage applied to and across a pass transistor in a CMOS chip.
2. Prior Art
A pass transistor, e.g., an N-channel transistor MN1, in an integrated circuit CMOS chip has its source connected to one node IO1 and its drain connected to another node IO2 with its gate driven by a voltage V1 on a third node N1 (see FIG. 1). A V.sub.gs drop is required to keep transistor MN1 ON, so that if node IO1 is driven above VCC, the voltage on node IO2 should be limited to VCC-VTXNS5, where VTXNS5 is the transistor threshold voltage with the bulk connection tied to VCC. However, if VTXNS5 is not high enough, the voltage on IO2 will go higher than a design required limit drawing excess charge through MN1. Further, if IO1 is driven high very quickly, for instance, from 0 to 5 volts with a signal that has a fast rise time, then the capacitive coupling between IO1 and node N1, due to the overlap capacitance of MN1, will drive up the voltage V1 on node N1. This condition will allow more charge to flow through MN1 and hence the voltage on IO2 will also rise and may end up at a voltage considerably higher than anticipated. Under such circumstances, there is no mechanism, other than leakage, e.g., reverse-biased diode leakage through the drain of MN1, for the charge on IO2 to be removed even if the voltage on the gate of MN1 subsequently decays to a lower value.